Cronologic Ndigo Crate Manual de usuario descargar pdf (Pagina 13)

TKDN-SP6-16 TKDN-SP6-45 EXPARTAN-6T

I/O 数

User LEDs

Push switches

Expansion I/O

Clock

OS for development

Memory

Size

FPGA

Conﬁguration times

Board size

FPGA development env.

18ｋB Block Memory

Maximum speed

SPI ROM

Feature

Part number

Feature

Part Number

Configuration

DSP48 Slices

Logic cells

Part Number

DDR2 SDRAM

Interface

USB

PCI Express

SATA

M25P32 (Numonyx) (32Mbit )

It can store FPGA coﬁguration data and user data.

128MByte, 16bit wide data

8bank

1Gbit

400Mb/sec (6.4Gbps)800Mb/sec (6.4Gbps)

64MByte, 8bit wide data

4bank

512Mbit

HYB18T512800BF-2.5 (Quimonda)

Pin placement is compatible for MCB of Spartan-6

116

43661

14579

72 ㎜ x 50 ㎜

・USB2.0 HighSpeed (480Mbps) * Eﬀective speed is IN:40MBytes/sec,OUT:30MBytes/sec

・Available for FPGA conﬁguration, communication for user application and power supply.

・Device driver , API DLL, and control software are provided.

Usable immediately. Deep knowledge for USB is unnecessary .

・Maximum 32 boards are controllable from 1 PC.

・Control libraries for LabView and MATLAB is available for free download.

・Controlable from Microsoft Excel with VBA.

About 10 seconds

Microsoft Windows 2000/XP/Vista/7 (32bit)

・FPGA configuration and SPI ROM programming is available from our special tool.

・Advanced FPGA debuging by MITOUJTAG (other selling) is supported .

（programing with iMPACT and debugging with ChipScope via XILINX platform-USB is available）

HYB18T1G160BF-5

90 ㎜ x 69 ㎜（Low proﬁle）

About 3 seconds

XC6SLX45T-2FGG484CXC6SLX45-３CSG324CXC6SLX16-３CSG324C

・2x 40 Pin headders 2.54mm pitch

XILINX ISE11.2 or later (ISE12.2 is recommended) ※Free ISE Web PACK available !

・VCCO separable for Bank2

・

30 pairs LVDS signal available

On board USB-JTAG

supported

・29 pairs LVDS signal available

・On board X-tal oscillator 50MHz

・Clock-in from Expansion I/O

・48MHz oscillator for USB

・150MHz LVDS oscillator for SATA

※Contents in this page is a speciﬁcation on November 2010. This may be improved without a notice for the improvement of product quality and the function.

・ x1 lane conﬁguration.

Gen1 (2.5Gbps)

・ PCIe card edge and external cabling

supported

・ Device driver, API and control

software provided

Usable immediately without deep

knowledge

・ PCIe-DMA IP core which wraps

Spartan-6LXT Integrated-EndPoint

is provided.

・

SATA connectors (device and host)

are equipped

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 75 76

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Cronologic Ndigo Crate Manual de usuario Pagina 13

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