Cronologic Ndigo Crate Manual de usuario descargar pdf (Pagina 7)

1

G

bit

(

128 Mbyte

)

D

DR3

S

DRA

M

1

G

bit

(

128 Mb

y

te

)

D

DR3

S

DRA

M

16

b

it

s

1

6

b

it

s

9

(

-1

)

x xs

y

stem I

/O

s

52 x diff. I

/O

)

(

(104 x s.e. I/O)

5

(

+1

)

x s.e. I/O

s

Gigabit Ethernet

(PHY

s

i

ca

l

l

ayer

)

JTA

G

e

FU

S

E

*

Quad-SPI

SP

64

Mbit

(

8 Mbyte

)

Quad-SP

I

s

er

i

a

l

Fl

as

h

48-bit EPR

OM

(

MAC address)

sw

i

tc

hi

n

g

r

e

g

u

l

ator

sw

i

tc

hi

n

g

r

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l

ator

lin

ea

r

re

g

ulato

r

watc

hd

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g

3

.

3

V

1

.5

V

1

.2

V

2.

5

V

Vccaux

x

r

eset

2

00

MH

z

d

i

ff

.

osc

.

1

25

MHz

E

t

h.

PHY

Xilinx FP

GA

S

partan-6 L

X

(

2

5

/

45

/

7

5*

/

1

00*

)

Key Features

t

I

n

d

ustr

i

a

l

-gra

d

e

Xilinx Spartan-6 LX

FPGA module (LX

X

45

,

LX

100

,

LX

1

5

0

)

t

1

0

/

100

/

1000

G

bit Ethernet transceiver

(

PHY

)

t

2

× 16-bit-wide 1

G

bit-large

D

DR3

S

DRAM

t

L

arge

S

PI Flash memory

(

for conﬁguration and operation

)

a

ccess

ibl

e t

h

roug

h

:

t

B

2B connector

(S

PI direct

)

t

F

P

G

A

t

J

TA

G

port

(S

PI indirect

)

t

gi

ga

bi

t

E

t

h

ernet transce

i

ver

t

F

P

G

A conﬁguration through:

t

B

2

B

connector

t

J

TA

G

port

t

S

PI Flash memory

t

U

p to

52

diff

erent

i

a

l

,

up

t

o

109

s

i

ng

l

e-en

d

e

d

(

+ 1 dual-

p

urpose

)

FP

G

A I

/O

pins available on B2B strips

t

Pl

ug-on mo

d

u

l

e w

i

t

h

two 100-p

i

n

hi

g

h

-spee

d

h

ermap

h

ro

di

t

i

c

s

tac

ki

ng str

i

ps

t

3

.0

A

x 1.2

V

power ra

il

t

1

.0

A

x 1.5

V

power ra

il

t

1

25 MHz re

f

erence clock signal

t

e

FU

S

E bit-stream encryption

(

LX100 or larger

)

t

1

user

LED

t

E

venly-spread supply pins

f

or good signal integrity

t

F

ootprint for single-ended custom oscillator

(

optional

)

Development Suite

A hardware development plat

f

orm is available. Latest

documentation, design support

ﬁ

les and so

f

tware development

suite are available

f

or download

f

ree o

f

charge

:

t

U

ser manua

l

, app

li

cat

i

on note

s

t

S

chematics, assembly diagrams,

C

AD library ﬁle

s

t

Fi

rmware

t

IP-cores

(

DMA, 1-Wire

)

t

Programming tools

(S

PI Flash

)

t

Re

f

erence bit-stream

s

t

Re

f

erence design

s

t

Reference Xilinx MicroBlaze system

(

EDK

).

Assembly Options

m

odu

l

e

c

l

ass

k lo

g

ic cell

s

MA

Cs

T

E

0600

LX4

5

43

58

TE

0600

LX

100 101 18

0

T

E

0600

LX1

50

14

71

80

C

ustom assembly options for cost or performance optimization

are ava

il

a

bl

e upon request

.

engineered for free Xilinx W

eb

PA

CK

embedded

p

rocesso

r

www.trenz-electronic.de

/

te060

0

7

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