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2.4.2 Trigger Blocks

The Ndigo250M-14 records analog wave forms using zero suppression. Whenever a relevant

waveform is detected, data is written to an internal FIFO memory. Each ADC channel has

one trigger block determining whether data is written to the FIFO. The parameters are set in

Structure ndigo trigger block(See chapter 3.4.3 on page 35).

Each trigger block consists of two independent units that check the incoming raw data stream

for trigger conditions (Fig. 2.9 on page 9). Users can specify a threshold and can choose whether

triggering happens whenever incoming data is below or above the threshold (level triggering) or

only in the moment data crosses the threshold (edge triggering).

A gate length can be set to extend the trigger window. Furthermore, if users choose precursor

values > 0, the trigger unit will start writing data to the FIFO precursor samples before the

trigger event.

When using edge triggering, all packets have the same length (Figure 2.10 on page 11):

precursor + length + 1 cycles. For level triggering, the packet length is data dependent (Figure

2.11 on page 11).

For the Ndigo250M-14 the triggering is sample accurate.

If retriggering is active, the current trigger window is extended if a trigger event is detected

inside the window. The extension lasts length cycles after the last sample trigger event.

A trigger block can use several input sources:

the 8 trigger decision units of all four ADC channels (Figure 2.12 on page 12)

the GATE input (Figure 2.13 on page 12)

the TRIGGER input (Figure 2.13 on page 12)

a function trigger providing random or periodic triggering (Section 2.4.4 on page 16)

triggers originating from other cards connected with the sync cable or from the Ndigo

Extension card (BUS0, BUS1, BUS2, BUS3)

A second set of trigger units for the digital inputs TRIGGER, GATE, BUS0, BUS1, BUS2,

and BUS3 that is set in hardware to positive edge triggering. This set of triggers is not

available as inputs for the gate blocks.

Trigger inputs from the above sources can be combined using logical “OR” (Figure 2.14 on

page 13) by setting the appropriate bits in the trigger blocks source mask.

Triggers can be fed into the gating blocks described on page 14 (Figure 2.15). Gating blocks

can be used to block writing data to the FIFO. That way, only zero suppressed data occurring

when the selected gate is active is transmitted. This procedure reduces PCIe bus load even

further (Figure 2.15).

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