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T = 1 + M + [1...2

] (3.1)

clock cycles.

0 ≤ M < 2

(3.2)

0 ≤ N < 32 (3.3)

There is no enable or reset as the usage of this trigger can be conﬁgured in the trigger block

channel source ﬁeld.

int divisor

The 500MHz base clock is divided by this divisor to create the rsampling frequency. Valid values

are 2 to 32 for the Ndigo250M and 4 to 32 for the Ndigo125M.

int high gain[2]

If set to 1 the input gain is boosted by 3.5dB. Gain[0] modiﬁes channels 0 and 1, gain[1] modiﬁes

channels 2 and 3.

int ﬁne gain[2]

Gain setting in steps of 0.5dB from 0 (0dB) to 12 (6.0dB). Gain[0] modiﬁes channels 0 and 1,

gain[1] modiﬁes channels 2 and 3.

int gain correction[2]

Gain setting in steps of 0.05dB from 0 (0dB) to 10 (0.5dB). Gain[0] modiﬁes channels 0 and 1,

gain[1] modiﬁes channels 2 and 3.

3.4.2 Structure ndigo trigger

short threshold

Sets the threshold for the trigger block within the range of the ADC data of -32768 and +32768.

For trigger indices NDIGO TRIGGER TDC to NDIGO TRIGGER BUS3 PE the threshold is ig-

nored.

ndigo bool t edge

If set this trigger implements edge trigger functionality else this is a level trigger.

For trigger indices NDIGO TRIGGER AUTO and NDIGO TRIGGER ONE this is ignored.

For trigger indices NDIGO TRIGGER TDC PE to NDIGO TRIGGER BUS3 PE this must be set.

ndigo bool t rising

If set trigger on rising edges or when above threshold.

cronologic GmbH & Co. KG 34 Ndigo250M-14 User Guide

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Cronologic Ndigo Crate Guía de usuario Pagina 38