Cronologic Ndigo Crate Guía de usuario descargar pdf (Pagina 40)

#deﬁne NDIGO TRIGGER SOURCE GATE 0x00000200

#deﬁne NDIGO TRIGGER SOURCE BUS0 0x00000400

#deﬁne NDIGO TRIGGER SOURCE BUS1 0x00000800

#deﬁne NDIGO TRIGGER SOURCE BUS2 0x00001000

#deﬁne NDIGO TRIGGER SOURCE BUS3 0x00002000

#deﬁne NDIGO TRIGGER SOURCE AUTO 0x00004000

#deﬁne NDIGO TRIGGER SOURCE ONE 0x00008000

#deﬁne NDIGO TRIGGER SOURCE TDC PE 0x01000000

#deﬁne NDIGO TRIGGER SOURCE GATE PE 0x02000000

#deﬁne NDIGO TRIGGER SOURCE BUS0 PE 0x04000000

#deﬁne NDIGO TRIGGER SOURCE BUS1 PE 0x08000000

#deﬁne NDIGO TRIGGER SOURCE BUS2 PE 0x10000000

#deﬁne NDIGO TRIGGER SOURCE BUS3 PE 0x20000000

int gates

#deﬁne NDIGO TRIGGER GATE NONE 0x0000

#deﬁne NDIGO TRIGGER GATE 0 0x0001

#deﬁne NDIGO TRIGGER GATE 1 0x0002

#deﬁne NDIGO TRIGGER GATE 2 0x0004

#deﬁne NDIGO TRIGGER GATE 3 0x0008

double minimum free packets;

This parameter sets how many packets are supposed to ﬁt into the on-board FIFO before a new

packet is started after the FIFO was full, i.e. a certain amount of free space in the FIFO is

demanded before a new packet is written after the FIFO was full. As a measure for the packet

length the gatelength set by the user is used. The on-board algorithm checks the free FIFO

space only in case the FIFO is full. Therefore, if this number is 1.0 or more at least every second

packet in the DMA buﬀer is guaranteed to have the full length set by the gatelength parameters.

In many cases smaller values will also result in full length packets. But below a certain value

multiple packets that are cut oﬀ at the end will show up.

3.4.4 Structure ndigo gating block

ndigo bool t negate

Invert output polarity. Defaults to false.

ndigo bool t retrigger

Defaults to false. If retriggering is enabled the timer is reset to the value of the start parameter

whenever the input signal is set while waiting to reach the stop time.

ndigo bool t extend

Defaults to true. If set, a gate is created with the set timing from the ﬁrst occurrence of the

input trigger even for short gates. If not set, the input signal must persist for the gate to be

cronologic GmbH & Co. KG 36 Ndigo250M-14 User Guide

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 56 57

Sin comentarios

Cronologic Ndigo Crate Guía de usuario Pagina 40