Cronologic Ndigo Crate Guía de usuario descargar pdf (Pagina 35)

Alert ﬂags from the system monitor and temperature sensor. Bits 0 to 3 are measured by the

system monitor of the FPGA. Bits 4 and 5 are provided by an external temperature sensor.

Bit 0 : FPGA temperature alert (> 85

◦

Bit 1 : Internal FPGA voltage out of range (< 1.01V or > 1.08V )

Bit 2 : FPGA auxiliary voltage out of range. (< 2.375V or > 2.625V )

Bit 3 : FPGA temperature critical (> 125

◦

Bit 4 : FPGA temperature alert (> 90

◦

Bit 5 : FPGA temperature critical (> 100

◦

double voltage aux

Auxiliary FPGA voltage, nominal 2.5V

double voltage int

Internal FPGA voltage, nominal 1.03V

double fpga temperature

◦

C measured on die by internal system monitor.

double pcie pwr mgmt

Set to 0 if link power management is turned oﬀ.

int pcie link width

Number of PCIe lanes that the card uses. Should be 8. Lower values possible if the mainboard

does not support 8 lanes in the slot chosen.

int pcie max payload

Maximum size in bytes for one PCIe transaction, depends on system conﬁguration.

3.3.5 Structure ndigo slow info

This structure contains data that requires many milliseconds to retrieve.

int size

The number of bytes occupied by the structure.

int version

A version number that is increased when the deﬁnition of the structure is changed. The incre-

ment can be larger than one to match driver version numbers or similar. Set to 0 for all versions

up to ﬁrst release.

double FPGA temperature

ADC temperature in

◦

C measured on die by external temperature sensor.

double board temperature

◦

C. Measured by external temperature sensor.

cronologic GmbH & Co. KG 31 Ndigo250M-14 User Guide

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Cronologic Ndigo Crate Guía de usuario Pagina 35